Category: Uncategorized

We are excited to invite all of you to attend the fourth TECHNICAL TALK, TECH-TALK, in the INDUSTRY EXPOSURE SERIES. We are hosting this event with
TendemLaunch https://www.tandemlaunch.com/en/ and LATYS https://www.latys.ca/
In this event, speakers from LATYS will share their experience with TandemLaunch. The speakers from TandemLaunch will also talk about its program
near the end of the event.
We will be giving out one of Amazon(Canada) or UberEats(Canada) GIFT-CARDS (CAD 15 each) to the attending graduate students of the ECE department of the University of Toronto who register and attend the event for more than 30 minutes.
Please find more information about the event below.
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EVENT INFORMATION
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DATE        : Thursday, Jul 8, 2021
TIME        : 11 AM – 12 PM
REG. LINK: https://utoronto.zoom.us/meeting/register/tZwtc–srzsuGNGKKlRNzya97SnpTTssY-3S
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TITLE:
How To Be An Entrepreneur? TandemLaunch
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ABSTRACT:
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TandemLaunch is a unique startup foundry and seed fund based in Montreal. Through investing in highly qualified people, TandemLaunch works with tech entrepreneurs to build companies around acquired university technologies.
Learn about TandemLaunch through the experience of one of our successful ventures: Artmiz Golkaramnay & Gursimran Singh Sethi, the co-founders of LATYS.
LATYS is leveraging groundbreaking research in the area of reconfigurable metasurfaces to create the world’s first non-reciprocal wireless relay system that breaks the current rules of antenna design. LATYS proprietary technology is built using non-resonant metasurfaces that allow us to build ultra-compact wireless relays that are dynamically reconfigurable and are inherently immune to interference, multipath fading, and noise.
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SPEAKER BIO.:
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ARTMIZ GOLKARAMNAY, Co-founder and Product Lead at LATYS
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Artmiz is the co-founder and product lead of LATYS, a Montreal based startup. She earned her BS in Electrical and Computer Engineering at Norwich University (Vermont, USA) and her MASc in Electrical and Computer Engineering at Concordia University (Montreal, Canada).
Artmiz’ initial research had been focused in diverse areas of circuit design, cryptography, and mathematics. Her latest research was focused on improving 5G mmWave networks using Reinforcement Learning techniques.
With her love for engineering and passion for the wireless communication industry, she has contributed to several professional organizations in different capacities. She served as the collegiate chapter president of Society of Women Engineers, chair of IEEE, and president of Tau Beta Pi.
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GURSIMRAN SINGH SETHI, Co-founder & Tech Lead at LATYS
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Gursimran is an antenna and Metamaterial design expert. He is currently the technical lead at LATYS which is focused on designing groundbreaking non-reciprocal metasurface antennas that will change the future of the wireless industry.
Gursimran earned his BEng (Hons) degree from the Hong Kong University of Science and Technology and his MASc degree from the University of Toronto in 2019 where he developed state-of-the art low-profile reconfigurable antennas for Thales Alenia Space.
His research has been focused on developing novel microwave and mm-wave antennas for Satellite, IoT, and 5G applications. He has held prestigious research and work positions at Princeton University and Apple and has been a recipient of multiple Canadian awards and international grants by the Antennas and Propagation Society of the IEEE.
As an active member of the IEEE, Gursimran regularly contributes to academic conferences and journal articles pertaining to next generation reconfigurable antennas. He has also filed for two US patents for his work in the area of reconfigurable antennas.
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MADELEINE RAUTE, HR Advisor at TandemLaunch
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VALENTINE DENIS, HR Intern at TandemLaunch
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For more information, welcome to the Industry Exposure Program page of the ECEGSS at the University of Toronto.

Through the industry exposure series, we facilitate a platform for students and industries to engage with each other in a mutually beneficial manner.

https://www.notion.so/Industry-Exposure-Program-f3d25db2e0634e75adaa7b0e7e6a9f86

We are excited to invite all of you again to attend the third TECHNICAL TALK, TECH-TALK, in the INDUSTRY EXPOSURE SERIES.
We are hosting this event with Cerebras, https://cerebras.net/
Information about INTERNSHIP & FULL-TIME EMPLOYMENT OPPORTUNITIES
at the company will follow the event.
We will be giving out one of amazon(Canada) or UberEats(Canada) GIFT-CARDS (CAD 15 each) to the attending students who register and attend the event for more than 30 minutes.
Please find more information about the event below.
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EVENT INFORMATION
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DATE        : Thursday, Jun 10, 2021
TIME        : 11 AM – 12 PM
REG. LINK   : https://utoronto.zoom.us/meeting/register/tZUpfuCopjMqG91xCU3cZByrcHqHfwCc0yP2
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TITLE:
Cerebras Systems: A Systems Approach to Deep Learning
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ABSTRACT:
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The rise of Machine Learning workloads has spurred new interest in specialized hardware architectures, which offer significant improvements in performance and power efficiency. However, a substantial challenge faced by these architectures is providing a highly productive software interface, which also unlocks the hardware’s full performance.
In this talk, we will provide an overview of the software stack we’re developing at Cerebras to program the Wafer Scale Engine (WSE) 2. The WSE2 is the largest chip ever built, with 850,000 AI-optimized cores, and orders of magnitude more compute, memory, and interconnect bandwidth than single die offerings. We’ll focus on some of the challenging and interesting problems, which we’re solving to make the WSE2’s massive performance accessible and easy to use. We will also cover Machine Learning on the Wafer-Scale Engine.
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SPEAKER BIO.:
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KEVIN MURRAY
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Kevin E. Murray is a Member of Technical Staff at Cerebras Systems in Toronto. He received his PhD in Electrical and Computer Engineering from the University of Toronto in 2020. He was previously the lead developer of the Verilog to Routing (VTR) project, a visiting Research Assistant at Imperial College London, and has worked on digital design flows at Advanced Micro Devices (AMD). His research interests include Computer Aided Design (CAD) algorithms, and architecture for Machine Learning accelerators and FPGAs.
NATALIA VASSILIEVA
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Natalia Vassilieva is the Director of Product at Cerebras. Her focus is machine learning and artificial intelligence, analytics, and application-driven software-hardware optimization and co-design. Previously, Natalia has been a Sr. Research Manager at Hewlett Packard Labs, where she led the Software and AI group and served as the head of HP Labs Russia from 2011 till 2015. Prior to HPE, she was an Associate Professor at St. Petersburg State University and worked as a software engineer for different IT companies. Natalia holds a PhD in computer science from St. Petersburg State University.
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More Company Info.:
Info on 2nd gen product line here: https://www.anandtech.com/show/16626/cerebras-unveils-wafer-scale-engine-two-wse2-26-trillion-transistors-100-yield
Collaboration with AstraZeneca: https://larslynnehansen.medium.com/accelerating-drug-discovery-research-with-new-ai-models-a-look-at-the-astrazeneca-cerebras-b72664d8783
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Cheers
ECEGSS

Hi ECE grads!

The ECEGSS is hosting a virtual trivia night on June 3 at 6 pm. Come alone or with a group of friends to test your skills! All participants will receive a $15 dollar Amazon or Uber Eats gift card and the team that takes home the top prize will receive an additional $15 dollars each!

Register for the event below:
https://utoronto.zoom.us/meeting/register/tZwuc-CsqTsrGNZcoRBnYYFXXrjtpo_3Iac9

See you on Thursday!

ECEGSS exec team

Hello Hello ?

We are thrilled to share an exciting event. ECEGSS is hosting a bi-weekly running/biking/walking event to PROMOTE health and wellness. All you have to do is participate and achieve some easily achievable goals to win one of the many $20 Amazon Gift Cards!

Targets in a period of two weeks (May 27th – June 12th)

2 hours of biking
1 hour of running and or
4 hours of walking.

To claim your gift(s), we suggest using a fitness app, preferably Strava, or any fitness tracker, such as Fitbit, Apple Watch, Garmin, etc. We will be collecting data to modify our targets and gifts in the coming events, so it is not only to justify our claim for the gifts but also to keep track of your progress.

You‘ll be responsible for making sure you provide authentic information as requested in the following link: https://forms.gle/hibWYSxP8uJUi88t9

Cheers
ECEGSS
https://www.instagram.com/ecegssofficial/
https://twitter.com/UofTECEGSS

We are excited to invite all of you again to attend the second TECHNICAL TALK, TECH-TALK, in the INDUSTRY EXPOSURE SERIES.

We are hosting the second event with GROQ on May 13, 202, 11 AM – 12 PM.
The presenters will also do a short DEMO of their product.
Information about FULL-TIME EMPLOYMENT OPPORTUNITIES at the company will follow the event.

We will be giving out one of Amazon (Canada) or UberEats (Canada) GIFT-CARDS (CAD 15 each) to the attending students who register and attend the event for more than 30 minutes. Please find more information about the event below.
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EVENT INFORMATION
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DATE        : Thursday, May 13, 2021
TIME        : 11 AM – 12 PM
REG. LINK   : https://utoronto.zoom.us/meeting/register/tZcvcu-tqDooG9XkKsWL08UGOKdVZ4LZy3ai
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AGENDA:
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11:00-11:20 – Andrew Ling, GM and SW Director, presents on Groq and Path to Win AI Space
11:20-11:35 – Groq Demo by Mark Wong-VanHaren, Visualizer and Scheduler viewer, and presents roles within his organization
11:35-11:40 – Jennifer Hwang presents roles and type of people she’s looking for in the HW organization
11:40-11:50 – Q&A
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TITLE:
Think Fast!  A simplistic approach to tackling machine learning and compute at the end of Moore’s Law.
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ABSTRACT:
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Recently closing a $300M funding round, one of the largest funding rounds in AI chip history, Groq has invented an entirely new approach to solve deep learning workloads and HPC.  Based on dataflow and streaming concepts, the Groq Tensor Streaming Processor is able to achieve a 4x improvement compared to other model GPUs and accelerators.
The TSP is built based on two key observations: (1) machine learning workloads exhibit abundant data parallelism, which can be readily mapped to tensors in hardware, and (2) a deterministic processor with a stream programming model enables precise reasoning and control of hardware components to achieve good performance and power efficiency. The TSP is designed to exploit parallelism inherent in machine-learning workloads including instruction-level, memory concurrency, data and model parallelism. This guarantees determinism by eliminating all reactive elements in the hardware, for example, arbiters and caches. Early ResNet50 image classification results demonstrate 20.4K processed images per second with a batch size of one.
Our first ASIC implementation of the TSP architecture yields a computational density of more than 1 TOp/s per square mm of silicon. This TSP is a 25x29mm 14nm chip operating at a nominal clock frequency of 900MHz. The TSP also demonstrates a novel hardware-software approach to achieve fast yet predictable performance on machine-learning workloads within a desired power envelope. This architecture can be deployed across a broad range of applications, from ML to HPC within the datacenter, where low-latency and high-throughput are critical facets of total cost of ownership.
In this talk, we will explore the Groq TSP and help you understand how its simplistic approach to compute yields significant efficiency for acceleration.
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Speaker Bio.:
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ANDREW LING : General Manager and SW Director
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Andrew Ling received his Ph.D. from the University of Toronto in 2009.  After that, he spent most of his time at Altera, which was later acquired by Intel.  His primary focus at Altera/Intel was the development of the OpenCL compiler and later on, moved into CNN acceleration for FPGAs. He now leads the Groq Canada Design Centre, where they are focused on developing scalable ML software and compiler tools for the Groq TSP.
JENNIFER HWANG :: Director, Hardware Engineering
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Jen is an engineer at heart. She has spent her entire career building ASICs, with over 30 successful tape-outs under her belt. Starting at MIT, Jennifer graduated with her Masters and Bachelors in Electrical Engineering. No stranger to startups, she was a part of Silicon Spice startup, which was acquired by Broadcom. Jen became a Director of Engineering responsible for Broadcom’s cellular processor division for hardware verification with a multi-site global team. At Groq, she is leading the Hardware verification team creating ASICs for machine learning. Specifically, she loves to roll up her sleeves and up to her elbows in the details of how things work. In her free time, she supports her family ? reading, skiing, and serving as a parent-volunteer for her two growing kids at school.
MARK WONG-VANHAREN :: Technical Lead, Groq Tools
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Mark has 30 years experience in software development. He co-founded Excite.com, was CTO of ecommerce site Glyde, and served as VP Ramp;D at Wordnik. Over the years, he’s designed and built a wide range of tools and products, including: a special-purpose search engine, a columnar DBMS, a category-best iPhone app, and a templating language and compiler. At Groq, Mark works on our compiler as well as developer tools. He especially enjoys taking complex problems and mercilessly simplifying, usually using a functional programming language. Mark studied computational linguistics at Stanford and maintains a strong interest in natural and programming languages. Outside of work, Mark enjoys tandem biking and creating music with his family band.
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More Company Info.:
https://www.forbes.com/sites/amyfeldman/2021/04/14/ai-chip-startup-groq-founded-by-ex-googlers-raises-300-million-to-power-autonomous-vehicles-and-data-centers/?sh=2000d63c65e3
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Regards
ECEGSS
https://www.instagram.com/ecegssofficial/
https://twitter.com/UofTECEGSS